A locally-built, LLM-digested index of recent arXiv papers in quant finance, geometry/topology, and statistical ML — keyword search served straight from SQLite on this machine.
Automated design of resilient, efficient DNNs for hardware.
New Ising models improve consensus clustering on specialized hardware.
Quantum algorithms for CVaR portfolio optimization face trade-offs between hardware coherence and expressibility.
We derive scaling laws for optimizing neural networks in hardware.
The ever increasing computational cost of Deep Neural Networks (DNN) and the demand for energy efficient hardware for DNN acceleration has made accuracy and hardware cost co-optimization for DNNs tremendously important, especially for edge devices. Owing to the large parameter space and cost of evaluating each paramete…
This paper tackles co-design of neural hardware and software to improve efficiency.
Recent breakthroughs in Deep Learning (DL) applications have made DL models a key component in almost every modern computing system. The increased popularity of DL applications deployed on a wide-spectrum of platforms have resulted in a plethora of design challenges related to the constraints introduced by the hardware…
DANCE optimizes neural network and accelerator design for faster, more efficient DNN execution.
Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timing-dependent plasticity (STDP) mechanism for learning. Existing hardware implementations of…
Hardware-accelerated RBM solves large combinatorial problems and integer factorization.
Optimized neural networks for Edge TPU achieve high accuracy in real-time image classification.
DJPQ optimizes neural network pruning and quantization for hardware efficiency.
Benchmark for DL inference on embedded HWAs, focusing on autonomous driving.
Novel NAS method balances performance and hardware metrics efficiently.
NASCaps automates CapsNet design for better accuracy and hardware efficiency.
Hardware accelerations of deep learning systems have been extensively investigated in industry and academia. The aim of this paper is to achieve ultra-high energy efficiency and performance for hardware implementations of deep neural networks (DNNs). An algorithm-hardware co-optimization framework is developed, which i…
With the rising popularity of machine learning and the ever increasing demand for computational power, there is a growing need for hardware optimized implementations of neural networks and other machine learning models. As the technology evolves, it is also plausible that machine learning or artificial intelligence wil…
PCNN prunes CNN weights efficiently for hardware acceleration.
An important linear algebra routine, GEneral Matrix Multiplication (GEMM), is a fundamental operator in deep learning. Compilers need to translate these routines into low-level code optimized for specific hardware. Compiler-level optimization of GEMM has significant performance impact on training and executing deep lea…
Efficient deep learning computing requires algorithm and hardware co-design to enable specialization: we usually need to change the algorithm to reduce memory footprint and improve energy efficiency. However, the extra degree of freedom from the algorithm makes the design space much larger: it's not only about designin…
Evolutionary strategy optimizes quantum circuit design and parameters.
Co-designing efficient machine learning based systems across the whole hardware/software stack to trade off speed, accuracy, energy and costs is becoming extremely complex and time consuming. Researchers often struggle to evaluate and compare different published works across rapidly evolving software frameworks, hetero…
The application of deep learning techniques resulted in remarkable improvement of machine learning models. In this paper provides detailed characterizations of deep learning models used in many Facebook social network services. We present computational characteristics of our models, describe high performance optimizati…
We present a design and implementation of the Thomas algorithm optimized for hardware acceleration on an FPGA, the Thomas Core. The hardware-based algorithm combined with the custom data flow and low level parallelism available in an FPGA reduces the overall complexity from 8N down to 5N serial arithmetic operations, a…
Chameleon optimizes neural network compilation for faster execution and shorter time.
ALF reduces network parameters and operations by 70% and 61%, respectively, on embedded hardware.
Galen algorithm compresses neural networks for specific hardware with reduced latency.
CoCoPIE shows AI can run on regular devices without special hardware.
HotNAS reduces AI search time from hundreds of GPU hours to less than 3 GPU hours.
Condensa programmatically optimizes neural network compression.
Optimizes neural networks by removing unnecessary layers, improving performance and speed.
A new penalty-free method optimizes portfolios without quantum annealing penalties.
Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-da…
Stealthy hardware Trojan exploits DLA architecture vulnerabilities.
BoTorch optimizes Bayesian optimization with MC methods and auto-differentiation.
Fully Homomorphic Encryption (FHE) refers to a set of encryption schemes that allow computations to be applied directly on encrypted data without requiring a secret key. This enables novel application scenarios where a client can safely offload storage and computation to a third-party cloud provider without having to t…
DONNA rapidly finds optimal neural networks across diverse spaces.
Graph neural networks have become increasingly popular in recent years due to their ability to naturally encode relational input data and their ability to scale to large graphs by operating on a sparse representation of graph adjacency matrices. As we look to scale up these models using custom hardware, a natural assum…
ERNet reduces CNN bandwidth needs for imaging tasks.
New KWS neural networks improve accuracy and power efficiency.
We implement a differentiable Neural Architecture Search (NAS) method inspired by FBNet for discovering neural networks that are heavily optimized for a particular target device. The FBNet NAS method discovers a neural network from a given search space by optimizing over a loss function which accounts for accuracy and …
Quantum annealing (QA) is a hardware-based heuristic optimization and sampling method applicable to discrete undirected graphical models. While similar to simulated annealing, QA relies on quantum, rather than thermal, effects to explore complex search spaces. For many classes of problems, QA is known to offer computat…
We introduce a learning-based framework to optimize tensor programs for deep learning workloads. Efficient implementations of tensor operators, such as matrix multiplication and high dimensional convolution, are key enablers of effective deep learning systems. However, existing systems rely on manually optimized librar…
Independent Component Analysis (ICA) is a dimensionality reduction technique that can boost efficiency of machine learning models that deal with probability density functions, e.g. Bayesian neural networks. Algorithms that implement adaptive ICA converge slower than their nonadaptive counterparts, however, they are cap…
Bayesian approach optimizes quantum circuits for noisy hardware.
OpEvo automates tensor operator optimization for better efficiency.
The omnipresence of deep learning architectures such as deep convolutional neural networks (CNN)s is fueled by the synergistic combination of ever-increasing labeled datasets and specialized hardware. Despite the indisputable success, the reliance on huge amounts of labeled data and specialized hardware can be a limiti…
Method predicts hardware resource usage by control software with guaranteed linear convergence.