On-device research index

arXiv research

A locally-built, LLM-digested index of recent arXiv papers in quant finance, geometry/topology, and statistical ML — keyword search served straight from SQLite on this machine.

168,695 papers · 148 categories

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4 results for “Verilog”

DAVE: Deriving Automatically Verilog from Englishcs.SE

Automates translating natural language to Verilog for digital design.

problem Manual translation of natural language specifications to Verilog is time-consuming and error-prone.

method Fine-tuned GPT-2 to derive Verilog from English, using a dataset of design tasks.

result GPT-2 achieved 94.8% correct translation across simple and abstract design tasks.

machine learning natural language processing digital design Verilog translation

2020-08-27abs ↗pdf ↗

Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorizationcs.LG

Paper proposes efficient BNN inference flow to reduce computation and memory costs.

problem High computation complexity in Bayesian Neural Networks (BNNs) limits deployment in power-constrained systems.

method Feature decomposition and memorization strategy to reduce computations and a memory-friendly computing framework to reduce memory overhead.

result Reduces computation by about half and energy consumption by 73% with 14% area overhead.

Bayesian Neural Networks Computation Reduction Feature Decomposition Memorization Hardware Implementation

2020-05-08abs ↗pdf ↗

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networkscs.ET

In this paper, a spintronic neuromorphic reconfigurable Array (SNRA) is developed to fuse together power-efficient probabilistic and in-field programmable deterministic computing during both training and evaluation phases of restricted Boltzmann machines (RBMs). First, probabilistic spin logic devices are used to devel…

2019-01-08abs ↗pdf ↗

Exposing Hardware Building Blocks to Machine Learning Frameworkscs.LG

The thesis explores how to integrate machine learning with hardware constraints.

problem Designing efficient neural networks for real-time processing with hardware limitations.

method Developed a library for training and converting sparse quantized neural networks to hardware.

result Demonstrated how to design and optimize neural networks for FPGA-based hardware.

Machine Learning Hardware Integration Neural Networks Quantization FPGA

2020-04-10abs ↗pdf ↗