New Ising models improve consensus clustering on specialized hardware.
problem Consensus clustering optimization problems.
method Formulated consensus clustering as Ising models and evaluated on specialized hardware.
result Our Ising models outperform existing techniques on consensus clustering.
Design automation optimizes deep learning models for various hardware.
problem Designing efficient deep learning models requires balancing algorithm and hardware.
method Proposes design automation techniques for specialized neural networks, including auto pruning and quantization.
result Learning-based automation achieves superior performance and efficiency compared to human design.
New KWS neural networks improve accuracy and power efficiency.
problem Maximizing accuracy and power efficiency in KWS systems.
method Hardware Aware Training (HAT) for LMU-based neural networks.
result Achieved state-of-the-art accuracy and low parameter counts.
CoCoPIE shows AI can run on regular devices without special hardware.
problem Real-time AI on mobile devices without special hardware.
method Compression-compiler co-design using CoCoPIE framework.
result Real-time AI applications on off-the-shelf mobile devices.
Specialized Deep Learning (DL) acceleration stacks, designed for a specific set of frameworks, model architectures, operators, and data types, offer the allure of high performance while sacrificing flexibility. Changes in algorithms, models, operators, or numerical systems threaten the viability of specialized hardware…
DANCE optimizes neural network and accelerator design for faster, more efficient DNN execution.
problem Challenges in optimizing neural network and accelerator design for efficient DNN execution.
method Differentiable approach to co-exploration of accelerator and network architecture design.
result Significantly shorter time to achieve superior accuracy and hardware cost metrics.
This paper tackles co-design of neural hardware and software to improve efficiency.
problem Designing efficient deep learning systems that consider both hardware and software optimizations together.
method Developed a constrained Bayesian optimization framework to automatically identify profitable design points in the joint hardware/software design space.
result Improved energy-delay product by 18% (ResNet) and 40% (DQN) over hand-tuned systems.
The omnipresence of deep learning architectures such as deep convolutional neural networks (CNN)s is fueled by the synergistic combination of ever-increasing labeled datasets and specialized hardware. Despite the indisputable success, the reliance on huge amounts of labeled data and specialized hardware can be a limiti…
Benchmarking TPU, GPU, and CPU for deep learning models.
problem Improving performance in deep learning training.
method ParaDnn benchmark suite for FC, CNN, and RNN models on TPU, GPU, and CPU.
result TPU, GPU, and CPU have unique strengths for different types of models.
ProxylessNAS directly optimizes neural architectures for large-scale tasks without proxy tasks.
problem Inefficient and costly neural architecture search for large-scale tasks.
method Directly learns neural architectures for large-scale tasks and hardware platforms without proxy tasks.
result Achieves better performance and efficiency than previous methods.
NASCaps automates CapsNet design for better accuracy and hardware efficiency.
problem Designing Capsule Networks is laborious and inefficient.
method Automated Neural Architecture Search (NAS) with Genetic Algorithm optimization.
result Jointly optimizes network accuracy and hardware efficiency.
Researchers show NN-based communication algorithms can be implemented on hardware without significant performance loss.
problem Reducing complexity and improving performance of NN-based communication algorithms for practical hardware implementation.
method Implementation of NN-based algorithms in fixed-point arithmetic with quantized weights on specialized hardware (FPGAs, ASICs).
result It is possible to implement NN-based algorithms in fixed-point arithmetic with quantized weights on hardware without significant performance loss.
This paper proposes a method to improve neural network quantization without retraining.
problem Handling outliers in quantized DNN weights and activations.
method Outlier Channel Splitting (OCS) which duplicates channels containing outliers and halves their values.
result OCS outperforms state-of-the-art clipping techniques with minimal overhead.
Sparse neural networks trained on commodity hardware achieve high accuracy for high-dimensional data.
problem Training and deploying modern ANNs on commodity hardware due to model size and data volume challenges.
method Introducing a technique to train truly sparse neural networks with fixed parameter count throughout training.
result Achieved higher accuracy than traditional methods and trained models with over 1 million neurons on a typical laptop.
GPyTorch accelerates GP inference using GPU hardware.
problem Inefficient GP inference tools on modern hardware.
method Blackbox Matrix-Matrix (BBMM) inference with GPU acceleration.
result Significant speedup in GP inference and approximations.
OverQ increases model accuracy by handling outliers in neural networks with minimal hardware changes.
problem Handling outliers in neural network weights and activations for low-precision quantization.
method Overwrite quantization (OverQ) that opportunistically increases bitwidth for activation outliers.
result OverQ can handle over 90% of outliers and achieve +5% ImageNet Top-1 accuracy on a quantized ResNet-50 at 4 bits.
EmBench evaluates DNN performance on various devices, identifying bottlenecks.
problem Understanding compatibility between DNN architectures and hardware.
method Systematic evaluation of state-of-the-art DNNs on commodity devices.
result Identifies bottlenecks in DNN architectures for different hardware.
New neuromorphic hardware learns MNIST digits efficiently.
problem Limited scalability and in-hardware learning in existing neuromorphic hardware.
method Low-cost scalable NoC-based SNN architecture with in-hardware STDP learning.
result Demonstrated learning capability of the hardware architecture.
Stealthy hardware Trojan exploits DLA architecture vulnerabilities.
problem Security of DLA deployed on hardware accelerators.
method Input Interception Attack (IIA) exploiting statistical properties of DLA outputs.
result Stealthy Trojan can trigger with some definiteness.
Benchmark for DL inference on embedded HWAs, focusing on autonomous driving.
problem Lack of comprehensive benchmarks for DL hardware.
method Developed a benchmark for inference on embedded HWAs, focusing on autonomous driving. Proposed new granularity, benchmark procedures, and performance indicators.
result Identifies mismatches between HWAs and DL models.
The paper tackles hardware efficiency in DL models, predicting and optimizing for latency and energy cost.
problem Predicting and optimizing hardware efficiency for DL models during inference.
method Develops predictive models and hardware-aware optimization techniques.
result Predictive models and optimization techniques can significantly improve hardware efficiency in DL applications.
TonY simplifies distributed ML job management.
problem Managing distributed ML jobs is complex and resource-intensive.
method TonY is an open-source orchestrator for distributed ML jobs.
result TonY simplifies distributed ML job management.
Automated design of resilient, efficient DNNs for hardware.
problem Designing reliable and efficient DNNs for hardware.
method Evolutionary optimization technique for DNN architecture design.
result Strong correlation between predicted and actual error resilience.
CLEANN detects and mitigates neural network Trojans without labeled data.
problem Trojans in embedded neural networks that bypass detection during inference.
method Dictionary learning and sparse approximation for identifying Trojan triggers, lightweight algorithm/hardware co-design.
result Efficient real-time execution on resource-constrained platforms, competitive attack resiliency.
Study feasibility of deep neural networks for Euro banknote classification.
problem Meeting special requirements for banknote classification by central banks.
method Training and testing deep neural networks on state-of-the-art GPU hardware for few classes and 0-class rejection.
result Deep neural networks can meet central bank requirements for banknote classification.
Quantum algorithms for CVaR portfolio optimization face trade-offs between hardware coherence and expressibility.
problem Quantum algorithmic resilience for CVaR portfolio optimization
method WS-QAOA vs. HE-VQNN
result WS-QAOA provides exact theoretical mapping but suffers from hardware decoherence, while HE-VQNN preserves hardware coherence but lacks expressibility.
Method predicts hardware resource usage by control software with guaranteed linear convergence.
problem Predicting time-varying hardware resource availability in control software.
method Path structured multimarginal Schrödinger bridge (MSBP) for learning stochastic resource usage.
result Guaranteed linear convergence to accurate prediction of hardware resource utilization.
Paper proposes a faster method for evaluating DNN hardware and software designs.
problem Reducing time for evaluating different DNN hardware and software designs.
method Using virtual hardware models to estimate DNN performance at the concept phase.
result Up to 92% accuracy in predicting DNN inference processing time.
SmartExchange trades memory for computation in neural networks.
problem Energy-efficient inference of deep neural networks.
method Algorithm-hardware co-design framework integrating sparsification, decomposition, and quantization.
result SmartExchange reduces energy consumption and improves performance.
We derive scaling laws for optimizing neural networks in hardware.
problem Optimizing the large parameter space of neural networks in hardware.
method Analytical derivation of scaling laws for Coordinate Descent optimization.
result Convergence is exponential and scales linearly with the number of neurons.
PABO optimizes DNN and hardware hyperparameters for efficient edge device acceleration.
problem Joint optimization of DNN accuracy and hardware cost for edge devices.
method Bayesian optimization with pseudo agent-based approach for memristive crossbar accelerators.
result PABO achieves significant speed-ups and superior performance compared to state-of-the-art methods.
New method bounds hardware noise without assumptions.
problem Estimating hardware noise without assumptions.
method Machine Learning and Conformal Prediction.
result Theoretical upper bounds of fidelity.
This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementatio…
Optimized neural networks for Edge TPU achieve high accuracy in real-time image classification.
problem Designing neural networks for hardware accelerators to achieve optimal performance.
method Hardware-aware neural architecture search and model customization for Edge TPU.
result Improved accuracy-latency tradeoff on Pixel 4's Edge TPU compared to existing models.
Ternary MobileNets improve efficiency and accuracy on constrained devices.
problem Efficiently compressing MobileNets for real-time applications on constrained devices.
method Per-layer hybrid filter banks for ternary quantization of MobileNets.
result 27.98% energy savings and 51.07% reduction in model size with comparable accuracy.
With the rising popularity of machine learning and the ever increasing demand for computational power, there is a growing need for hardware optimized implementations of neural networks and other machine learning models. As the technology evolves, it is also plausible that machine learning or artificial intelligence wil…
VegasFlow accelerates complex simulations across various hardware platforms.
problem Complex calculations and simulations requiring high-dimensional integrals.
method Monte Carlo integration techniques using Vegas algorithm and TensorFlow.
result Significantly faster performance on various hardware platforms.
Paper presents efficient algorithms for convolutional neural networks using Winograd minimal filtering.
problem Resource-efficient implementation of convolutional neural networks.
method Winograd minimal filtering trick applied to M-tap filters (M=3,5,7,9,11) for parallel hardware implementation.
result Approximately 30% reduction in multipliers for fully parallel hardware implementation.
Hardware-accelerated RBM solves large combinatorial problems and integer factorization.
problem Solving large combinatorial optimization and integer factorization problems.
method Logically synthesized RBM architecture, hardware acceleration, and efficient training methods.
result Hardware-accelerated RBM factorizes 16-bit numbers with 10000x speed and 32x power improvements.
A hybrid framework reduces ML complexity on edge devices.
problem Limited memory and energy on edge devices.
method Compressed data collection and tailored deep learning network.
result Significant reduction in computational complexity and memory.
New method speeds up sparse graph neural networks training on dense hardware.
problem Training sparse graph neural networks is slow on custom hardware.
method Inspired by sparse matrix optimization, developed techniques for dense hardware.
result Sparse graph neural networks trained in 13 minutes on 512-core TPUv2 Pod.
Quantum algorithm reduces CVA risk-neutral expectation estimation costs.
problem Reducing Monte Carlo sampling cost for CVA on real quantum hardware.
method Noise-aware quantum workflow combining market calibration, discretisation, and oracle construction.
result CABIQAE achieves lower classical post-processing runtime and more effective error exploitation.
Improves VQAs by balancing classical and quantum training resources.
problem Challenges in trainability and resource costs of VQAs on quantum hardware.
method Adopting HELIA Ansatz and combining classical and quantum methods for gradient estimation and training.
result Achieves higher accuracy and success rates in VQE and improved test accuracy in quantum phase classification.
Pipelined Backpropagation trains large models without batches efficiently.
problem Training large models efficiently on hardware with limited batch sizes.
method Fine-grained Pipelined Backpropagation with Spike Compensation and Linear Weight Prediction.
result Fine-grained Pipelined Backpropagation with a batch size of one matches the accuracy of SGD for multiple networks.
Binary and ternary weights simplify RNNs for mobile devices.
problem Complexity and memory intensity of RNNs on mobile devices.
method Learn binary and ternary weights during training.
result Significant memory saving and inference speedup on ASIC platform.
HotNAS reduces AI search time from hundreds of GPU hours to less than 3 GPU hours.
problem High time required for AI solution generation from scratch.
method HotNAS starts from a 'hot' state using pre-trained models and integrates compression during co-search.
result Reduces search time from 200 GPU hours to less than 3 GPU hours.
TensorFlow Probability MCMC toolkit improves MCMC efficiency for modern hardware.
problem Inefficient MCMC algorithms on modern hardware.
method Design and implementation of a new MCMC toolkit for TensorFlow.
result Improved MCMC efficiency on modern hardware.
A scalable DL benchmarking platform for evaluating and comparing models, frameworks, and hardware.
problem Lack of a uniform DL benchmarking platform for evaluating and comparing innovations.
method Identified 10 design features for a DL benchmarking platform, proposed MLModelScope, and implemented as an open-source project.
result Demonstrated how model, hardware, and framework selection affect accuracy and performance under different scenarios.