Stealthy hardware Trojan exploits DLA architecture vulnerabilities.
problem Security of DLA deployed on hardware accelerators.
method Input Interception Attack (IIA) exploiting statistical properties of DLA outputs.
result Stealthy Trojan can trigger with some definiteness.
New KWS neural networks improve accuracy and power efficiency.
problem Maximizing accuracy and power efficiency in KWS systems.
method Hardware Aware Training (HAT) for LMU-based neural networks.
result Achieved state-of-the-art accuracy and low parameter counts.
Method predicts hardware resource usage by control software with guaranteed linear convergence.
problem Predicting time-varying hardware resource availability in control software.
method Path structured multimarginal Schrödinger bridge (MSBP) for learning stochastic resource usage.
result Guaranteed linear convergence to accurate prediction of hardware resource utilization.
PipeMare enables efficient DNN training with minimal memory and pipeline sacrifices.
problem Sacrificing hardware efficiency to maintain statistical efficiency in pipeline parallel DNN training.
method PipeMare is a simple yet robust training method that tolerates asynchronous updates during pipeline parallelism without sacrificing pipeline utilization or memory.
result PipeMare achieves up to 2.7x less memory usage or 4.3x higher pipeline utilization compared to state-of-the-art synchronous PP training techniques.
The paper explores how to use neuromorphic hardware to mimic neural networks more closely.
problem Compensating for the limitations of analog neuromorphic hardware.
method Three strategies: auxiliary components, robust architectures, and training methods.
result Experimental results support the proposed methods for improving neuromorphic systems.
DJPQ optimizes neural network pruning and quantization for hardware efficiency.
problem Efficiently compress neural networks for hardware inference.
method Joint gradient-based optimization of pruning and quantization into a differentiable loss function.
result Significant reduction in Bit-Operations (BOPs) with minimal accuracy loss.
Galen algorithm compresses neural networks for specific hardware with reduced latency.
problem Finding optimal compression policies for neural networks on specific hardware.
method Reinforcement learning using pruning and quantization to optimize inference latency.
result Compressed ResNet18 for ARM processor reduced inference latency by 80%.
Efficient FPGA dropout algorithm reduces memory usage.
problem Overfitting in deep neural networks.
method Hardware-oriented dropout algorithm for FPGA implementation.
result Significant resource reduction in FPGA implementation.
This paper analyzes mobile device training of deep learning models.
problem Performance characterization of training deep learning models on mobile devices.
method Experiments on NVIDIA TX2, benchmark suite, and tools for performance analysis.
result Interesting performance problems and opportunities revealed.
VIBNN accelerates Bayesian Neural Networks on FPGAs for efficient inference.
problem Overfitting and small-data training issues in BNNs.
method Hardware accelerator design for variational inference on BNNs, using novel Gaussian random number generators.
result VIBNN achieves high throughput and energy efficiency on FPGA, matching software performance.
This paper uses machine learning to assist automation engineers in decision making.
problem Imperfect decision making by automation engineers leads to multiple iterations and increased time for software development.
method Defined challenges and proposed solutions using machine learning for automation engineering, including code classification, finding similar code snippets, and hardware selection.
result Paragraph embedding techniques achieved an F1-score of 72% for classifying automation using code snippets, and autoencoder models for hardware recommendation achieved p@3 and p@5 of 0.79 and 0.95, respectively.
AMPNet accelerates deep learning training on interconnected devices.
problem Training efficiency for dynamic neural networks with complex control flow.
method Asynchronous model-parallel training algorithm.
result AMP training achieves similar accuracy but faster convergence and shorter training times.
SELD-TCN improves sound event localization and detection efficiency.
problem Efficient sound event localization and detection on embedded hardware.
method Developed a novel temporal convolutional network (TCN) architecture.
result SELD-TCN outperforms state-of-the-art SELDnet on four datasets.
Paper proposes efficient BNN inference flow to reduce computation and memory costs.
problem High computation complexity in Bayesian Neural Networks (BNNs) limits deployment in power-constrained systems.
method Feature decomposition and memorization strategy to reduce computations and a memory-friendly computing framework to reduce memory overhead.
result Reduces computation by about half and energy consumption by 73% with 14% area overhead.
Quantum reservoir computing improves volatility forecasting.
problem Forecasting realized volatility in finance.
method Quantum reservoir computing with Ising Hamiltonian and feature selection.
result Quantum reservoir computing outperforms benchmarks in volatility forecasting.
XSP profiles ML models across hardware and software stacks.
problem Challenges in profiling ML model performance across different layers of the stack.
method XSP uses distributed tracing to aggregate data from various sources and introduces a leveled, iterative measurement approach.
result XSP provides insights into ML model execution not easily discernible otherwise.
DAWNbench evaluates deep learning training time vs. accuracy, revealing hardware underutilization.
problem Lack of standard evaluation metrics for deep learning performance.
method Introduced DAWNBench, a benchmark focusing on training time to achieve near-state-of-the-art accuracy.
result Training time to accuracy (TTA) is a reliable metric for comparing deep learning optimizations.
ProxylessNAS directly optimizes neural architectures for large-scale tasks without proxy tasks.
problem Inefficient and costly neural architecture search for large-scale tasks.
method Directly learns neural architectures for large-scale tasks and hardware platforms without proxy tasks.
result Achieves better performance and efficiency than previous methods.
A hardware-based reservoir computing system predicts time series with high speed and accuracy.
problem Processing time-dependent signals with high speed and accuracy.
method A hardware-based reservoir computing system using a field-programmable gate array (FPGA) for both the reservoir and output layers.
result Achieves comparable accuracy to software approaches but with a superior real-time prediction rate up to 160 MHz.
New neuromorphic hardware learns MNIST digits efficiently.
problem Limited scalability and in-hardware learning in existing neuromorphic hardware.
method Low-cost scalable NoC-based SNN architecture with in-hardware STDP learning.
result Demonstrated learning capability of the hardware architecture.
Benchmark for DL inference on embedded HWAs, focusing on autonomous driving.
problem Lack of comprehensive benchmarks for DL hardware.
method Developed a benchmark for inference on embedded HWAs, focusing on autonomous driving. Proposed new granularity, benchmark procedures, and performance indicators.
result Identifies mismatches between HWAs and DL models.
The paper tackles hardware efficiency in DL models, predicting and optimizing for latency and energy cost.
problem Predicting and optimizing hardware efficiency for DL models during inference.
method Develops predictive models and hardware-aware optimization techniques.
result Predictive models and optimization techniques can significantly improve hardware efficiency in DL applications.
Combines neural networks and logic circuits for interpretable, accurate, and cost-effective learning.
problem Lack of generalizability and interpretability in neural networks and high hardware cost in logic circuits.
method Trains a neural network, then translates it to random forests, and finally to AND-Inverter logic.
result The pipeline maintains greater accuracy and minimizes logic complexity.
New Ising models improve consensus clustering on specialized hardware.
problem Consensus clustering optimization problems.
method Formulated consensus clustering as Ising models and evaluated on specialized hardware.
result Our Ising models outperform existing techniques on consensus clustering.
DANCE optimizes neural network and accelerator design for faster, more efficient DNN execution.
problem Challenges in optimizing neural network and accelerator design for efficient DNN execution.
method Differentiable approach to co-exploration of accelerator and network architecture design.
result Significantly shorter time to achieve superior accuracy and hardware cost metrics.
SmartDeal reduces energy and storage costs for deep neural networks.
problem Heavy parameterization of deep neural networks leads to inefficient use of DRAM.
method SmartDeal decomposes weights into a small basis matrix and a structurally sparse coefficient matrix, quantized to power-of-2.
result Up to 2.44x energy efficiency improvement in inference and 10.56x reduction in training energy.
Automated design of resilient, efficient DNNs for hardware.
problem Designing reliable and efficient DNNs for hardware.
method Evolutionary optimization technique for DNN architecture design.
result Strong correlation between predicted and actual error resilience.
Hardware Trojans can fool neural networks, affecting security.
problem Security vulnerabilities in hardware optimized neural networks.
method Developed a framework for inserting malicious hardware Trojans in neural network classifiers.
result Trojans can fool neural networks with minimal impact, affecting 0.03% of neurons.
Efficient kernel methods for large datasets using GPU acceleration.
problem Handling large-scale nonparametric learning problems efficiently.
method Preconditioned gradient solver, GPU acceleration, parallelization, out-of-core linear algebra, numerical precision optimization.
result Dramatic speedups on datasets with billions of points, maintaining state-of-the-art performance.
Quantum algorithms for CVaR portfolio optimization face trade-offs between hardware coherence and expressibility.
problem Quantum algorithmic resilience for CVaR portfolio optimization
method WS-QAOA vs. HE-VQNN
result WS-QAOA provides exact theoretical mapping but suffers from hardware decoherence, while HE-VQNN preserves hardware coherence but lacks expressibility.
Paper proposes a faster method for evaluating DNN hardware and software designs.
problem Reducing time for evaluating different DNN hardware and software designs.
method Using virtual hardware models to estimate DNN performance at the concept phase.
result Up to 92% accuracy in predicting DNN inference processing time.
This paper tackles co-design of neural hardware and software to improve efficiency.
problem Designing efficient deep learning systems that consider both hardware and software optimizations together.
method Developed a constrained Bayesian optimization framework to automatically identify profitable design points in the joint hardware/software design space.
result Improved energy-delay product by 18% (ResNet) and 40% (DQN) over hand-tuned systems.
Design automation optimizes deep learning models for various hardware.
problem Designing efficient deep learning models requires balancing algorithm and hardware.
method Proposes design automation techniques for specialized neural networks, including auto pruning and quantization.
result Learning-based automation achieves superior performance and efficiency compared to human design.
Study binary data classification with low costs.
problem Classifying data represented in binary form.
method Proposes a framework with low computation and resource costs.
result Illustrates and analyzes the utility of the proposed approach.
SmartExchange trades memory for computation in neural networks.
problem Energy-efficient inference of deep neural networks.
method Algorithm-hardware co-design framework integrating sparsification, decomposition, and quantization.
result SmartExchange reduces energy consumption and improves performance.
We derive scaling laws for optimizing neural networks in hardware.
problem Optimizing the large parameter space of neural networks in hardware.
method Analytical derivation of scaling laws for Coordinate Descent optimization.
result Convergence is exponential and scales linearly with the number of neurons.
PABO optimizes DNN and hardware hyperparameters for efficient edge device acceleration.
problem Joint optimization of DNN accuracy and hardware cost for edge devices.
method Bayesian optimization with pseudo agent-based approach for memristive crossbar accelerators.
result PABO achieves significant speed-ups and superior performance compared to state-of-the-art methods.
New method bounds hardware noise without assumptions.
problem Estimating hardware noise without assumptions.
method Machine Learning and Conformal Prediction.
result Theoretical upper bounds of fidelity.
This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementatio…
This paper improves neural network training performance by optimizing concurrency and operation scheduling.
problem Managing and scheduling fine-grained operations in neural network training for high performance.
method Extending TensorFlow runtime to enable automatic concurrency control and scheduling, using performance modeling.
result Achieved 33% average performance improvement on neural network models, up to 49%.
Optimized neural networks for Edge TPU achieve high accuracy in real-time image classification.
problem Designing neural networks for hardware accelerators to achieve optimal performance.
method Hardware-aware neural architecture search and model customization for Edge TPU.
result Improved accuracy-latency tradeoff on Pixel 4's Edge TPU compared to existing models.
VegasFlow accelerates complex simulations across various hardware platforms.
problem Complex calculations and simulations requiring high-dimensional integrals.
method Monte Carlo integration techniques using Vegas algorithm and TensorFlow.
result Significantly faster performance on various hardware platforms.
Analog deep learning shows promise but faces scalability challenges.
problem Bottlenecks in deep neural networks' calculation and optimization.
method Evaluation of eight analog deep learning methodologies.
result Analog deep learning has potential for consumer-level applications but scalability remains an issue.
Paper presents efficient algorithms for convolutional neural networks using Winograd minimal filtering.
problem Resource-efficient implementation of convolutional neural networks.
method Winograd minimal filtering trick applied to M-tap filters (M=3,5,7,9,11) for parallel hardware implementation.
result Approximately 30% reduction in multipliers for fully parallel hardware implementation.
Hardware-accelerated RBM solves large combinatorial problems and integer factorization.
problem Solving large combinatorial optimization and integer factorization problems.
method Logically synthesized RBM architecture, hardware acceleration, and efficient training methods.
result Hardware-accelerated RBM factorizes 16-bit numbers with 10000x speed and 32x power improvements.
New method speeds up sparse graph neural networks training on dense hardware.
problem Training sparse graph neural networks is slow on custom hardware.
method Inspired by sparse matrix optimization, developed techniques for dense hardware.
result Sparse graph neural networks trained in 13 minutes on 512-core TPUv2 Pod.
Quantum algorithm reduces CVA risk-neutral expectation estimation costs.
problem Reducing Monte Carlo sampling cost for CVA on real quantum hardware.
method Noise-aware quantum workflow combining market calibration, discretisation, and oracle construction.
result CABIQAE achieves lower classical post-processing runtime and more effective error exploitation.
This paper evaluates ASR models on various co-processors, showing hardware acceleration benefits.
problem Lack of detailed training efficiency analysis for modern ASR systems.
method Developed a deep neural network ASR model and evaluated it on three co-processor platforms.
result Hardware acceleration yields good results even with less expensive equipment.