Research
On-device research index

arXiv research

A locally-built, LLM-digested index of recent arXiv papers in quant finance, geometry/topology, and statistical ML — keyword search served straight from SQLite on this machine.

168,742 papers · 148 categories

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74149223297 · Jun 202019922001200920172026
48 results for hardware errors

Quantum algorithm reduces CVA risk-neutral expectation estimation costs.

problem Reducing Monte Carlo sampling cost for CVA on real quantum hardware.
method Noise-aware quantum workflow combining market calibration, discretisation, and oracle construction.
result CABIQAE achieves lower classical post-processing runtime and more effective error exploitation.

StatQAT optimizes quantization for deep networks, reducing computational cost and memory usage.

problem Optimal quantization parameters selection for deep neural networks with diverse data distributions.
method Statistical error analysis framework for uniform and floating-point quantization, iterative and analytic quantizers designed for arbitrary and Gaussian-like distributions.
result Improved accuracy and stability in training low-precision neural networks.

A scalable DL benchmarking platform for evaluating and comparing models, frameworks, and hardware.

problem Lack of a uniform DL benchmarking platform for evaluating and comparing innovations.
method Identified 10 design features for a DL benchmarking platform, proposed MLModelScope, and implemented as an open-source project.
result Demonstrated how model, hardware, and framework selection affect accuracy and performance under different scenarios.

Survey of QML applications on near-term quantum devices.

problem Achieving quantum advantage on real-world applications.
method Analysis of supervised and unsupervised techniques, including encoding, ansatz structure, error mitigation, and gradient methods.
result Current QML implementations on quantum hardware face limitations but show potential for real-world applications.

Mitigates faults in DNNs by clipping activation values, improving their resilience.

problem Fault tolerance of DNNs in safety-critical applications.
method Clipping activation functions to reduce impact of faulty weights.
result Significant improvement in classification accuracy (68.92%) for fault mitigation.

Paper tackles noisy neural networks and proposes a method to enhance their robustness.

problem Noisy neural networks struggle with random continuous noise in weights.
method Knowledge distillation combined with noise injection during training.
result Models achieve up to twice greater noise tolerance.

We trained three Binarized Convolutional Neural Network architectures (LeNet-4, Network-In-Network, AlexNet) on a variety of datasets (MNIST, CIFAR-10, CIFAR-100, extended SVHN, ImageNet) using error-prone activations and tested them without errors to study the resilience of the training process. With the exception of …

2019-05-24abs ↗pdf ↗

Study shows BNN inference accelerators are vulnerable to soft errors, causing significant misclassification.

problem Vulnerability of BNN inference accelerators to soft errors affecting image classification accuracy.
method Fault injection experiments on CIFAR-10 and MNIST datasets to assess impact of soft errors.
result Accuracy of image classifier can drop by up to 76.70% in worst-case scenarios.

Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timing-dependent plasticity (STDP) mechanism for learning. Existing hardware implementations of…

2018-09-18abs ↗pdf ↗

A methodology for resilience analysis of Capsule Networks under approximation errors.

problem Resilience of Capsule Networks under approximation errors.
method Modeling and analyzing approximation errors in Capsule Networks' inference.
result Capsule Networks are more resilient to errors during dynamic routing than other stages.

Stealthy hardware Trojan exploits DLA architecture vulnerabilities.

problem Security of DLA deployed on hardware accelerators.
method Input Interception Attack (IIA) exploiting statistical properties of DLA outputs.
result Stealthy Trojan can trigger with some definiteness.

Recent machine learning methods use increasingly large deep neural networks to achieve state of the art results in various tasks. The gains in performance come at the cost of a substantial increase in computation and storage requirements. This makes real-time implementations on limited resources hardware a challenging …

2019-02-18abs ↗pdf ↗

New MIMO constellation design for noncoherent communications reduces hardware complexity.

problem Designing efficient MIMO constellations for noncoherent communications over fading channels.
method Geodesic curves of the Grassmann manifold for structured constellation design.
result Achieves comparable error performance to unstructured designs with reduced hardware complexity.

DANCE optimizes neural network and accelerator design for faster, more efficient DNN execution.

problem Challenges in optimizing neural network and accelerator design for efficient DNN execution.
method Differentiable approach to co-exploration of accelerator and network architecture design.
result Significantly shorter time to achieve superior accuracy and hardware cost metrics.

Recent breakthroughs in Deep Learning (DL) applications have made DL models a key component in almost every modern computing system. The increased popularity of DL applications deployed on a wide-spectrum of platforms have resulted in a plethora of design challenges related to the constraints introduced by the hardware…

2018-09-14abs ↗pdf ↗

Quantum algorithms for CVaR portfolio optimization face trade-offs between hardware coherence and expressibility.

problem Quantum algorithmic resilience for CVaR portfolio optimization
method WS-QAOA vs. HE-VQNN
result WS-QAOA provides exact theoretical mapping but suffers from hardware decoherence, while HE-VQNN preserves hardware coherence but lacks expressibility.

Method predicts hardware resource usage by control software with guaranteed linear convergence.

problem Predicting time-varying hardware resource availability in control software.
method Path structured multimarginal Schrödinger bridge (MSBP) for learning stochastic resource usage.
result Guaranteed linear convergence to accurate prediction of hardware resource utilization.

Paper proposes a faster method for evaluating DNN hardware and software designs.

problem Reducing time for evaluating different DNN hardware and software designs.
method Using virtual hardware models to estimate DNN performance at the concept phase.
result Up to 92% accuracy in predicting DNN inference processing time.

This paper tackles co-design of neural hardware and software to improve efficiency.

problem Designing efficient deep learning systems that consider both hardware and software optimizations together.
method Developed a constrained Bayesian optimization framework to automatically identify profitable design points in the joint hardware/software design space.
result Improved energy-delay product by 18% (ResNet) and 40% (DQN) over hand-tuned systems.

The implementation of artificial neural networks in hardware substrates is a major interdisciplinary enterprise. Well suited candidates for physical implementations must combine nonlinear neurons with dedicated and efficient hardware solutions for both connectivity and training. Reservoir computing addresses the proble…

2019-07-23abs ↗pdf ↗

A new model uses 'ghost units' to enable efficient backpropagation in deep neural networks.

problem How to achieve efficient backpropagation in deep neural networks with biological plausibility.
method Introduces 'ghost units' to cancel feedback, enabling efficient error backpropagation.
result Demonstrates that the model can approximate error gradients and achieve good performance on classification tasks.

GOBO compresses 99.9% of BERT model parameters to 3 bits, improving inference efficiency.

problem Efficient execution of attention-based NLP models, especially in terms of latency and energy consumption.
method GOBO quantizes 32-bit floating-point parameters to 3 bits without fine-tuning, using hardware compression and co-designed architectures.
result GOBO maintains model accuracy while significantly reducing inference latency and energy consumption.

We derive scaling laws for optimizing neural networks in hardware.

problem Optimizing the large parameter space of neural networks in hardware.
method Analytical derivation of scaling laws for Coordinate Descent optimization.
result Convergence is exponential and scales linearly with the number of neurons.

This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementatio…

2014-09-09abs ↗pdf ↗

Optimized neural networks for Edge TPU achieve high accuracy in real-time image classification.

problem Designing neural networks for hardware accelerators to achieve optimal performance.
method Hardware-aware neural architecture search and model customization for Edge TPU.
result Improved accuracy-latency tradeoff on Pixel 4's Edge TPU compared to existing models.

Recent advances in deep neural networks (DNNs) owe their success to training algorithms that use backpropagation and gradient-descent. Backpropagation, while highly effective on von Neumann architectures, becomes inefficient when scaling to large networks. Commonly referred to as the weight transport problem, each neur…

2019-01-30abs ↗pdf ↗

With the rising popularity of machine learning and the ever increasing demand for computational power, there is a growing need for hardware optimized implementations of neural networks and other machine learning models. As the technology evolves, it is also plausible that machine learning or artificial intelligence wil…

2018-06-14abs ↗pdf ↗

VegasFlow accelerates complex simulations across various hardware platforms.

problem Complex calculations and simulations requiring high-dimensional integrals.
method Monte Carlo integration techniques using Vegas algorithm and TensorFlow.
result Significantly faster performance on various hardware platforms.

Paper presents efficient algorithms for convolutional neural networks using Winograd minimal filtering.

problem Resource-efficient implementation of convolutional neural networks.
method Winograd minimal filtering trick applied to M-tap filters (M=3,5,7,9,11) for parallel hardware implementation.
result Approximately 30% reduction in multipliers for fully parallel hardware implementation.