On-device research index

arXiv research

A locally-built, LLM-digested index of recent arXiv papers in quant finance, geometry/topology, and statistical ML — keyword search served straight from SQLite on this machine.

168,742 papers · 148 categories

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4 results for “co-exploration”

DANCE: Differentiable Accelerator/Network Co-Explorationcs.LG

DANCE optimizes neural network and accelerator design for faster, more efficient DNN execution.

problem Challenges in optimizing neural network and accelerator design for efficient DNN execution.

method Differentiable approach to co-exploration of accelerator and network architecture design.

result Significantly shorter time to achieve superior accuracy and hardware cost metrics.

neural architecture search differentiable co-exploration hardware accelerator DNN execution non-linear relationships

2020-09-14abs ↗pdf ↗

The regret lower bound for communicating Markov Decision Processescs.LG

The paper improves regret lower bounds for communicating MDPs.

problem Regret lower bounds for communicating MDPs.

method Lower bound proof and optimization problem formulation.

result Regret lower bound becomes significantly more complex in communicating MDPs.

regret lower bound communicating MDPs co-exploration navigation constraints optimization problem

2025-01-22abs ↗pdf ↗

Asymptotically optimal regret in communicating Markov decision processescs.LG

Paper presents an algorithm for optimal regret in communicating Markov decision processes.

problem Achieving optimal regret in Markov decision processes with a communicating assumption.

method The algorithm explicitly tracks the constant K(M) to learn optimally, balancing exploration, co-exploration, and exploitation.

result The algorithm achieves asymptotically optimal regret

K(M) \log(T) + \mathrm{o}(\log(T))

for communicating Markov decision processes.

Markov decision processes asymptotically optimal regret communicating assumption exploration

2025-05-23abs ↗pdf ↗

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Taskscs.LG

Paper proposes NASAIC framework for co-designing neural architectures and heterogeneous ASICs.

problem Designing efficient neural architectures and ASICs for multiple tasks.

method Build ASIC templates and propose NASAIC framework for simultaneous design of architectures and ASICs.

result NASAIC ensures design specifications and maximizes accuracy with minimal performance loss.

Neural Architecture Search ASIC Design Heterogeneous Accelerators Neural Architectures DNNs

2020-02-10abs ↗pdf ↗