Researchers show NN-based communication algorithms can be implemented on hardware without significant performance loss.
problem Reducing complexity and improving performance of NN-based communication algorithms for practical hardware implementation.
method Implementation of NN-based algorithms in fixed-point arithmetic with quantized weights on specialized hardware (FPGAs, ASICs).
result It is possible to implement NN-based algorithms in fixed-point arithmetic with quantized weights on hardware without significant performance loss.
Graph neural networks improve charged particle tracking on FPGAs.
problem Charged particle trajectory determination in high interaction density conditions.
method Graph neural networks (GNNs) embedded in tracker data as graphs, classifying edges as track segments.
result GNNs implemented on FPGAs for charged particle tracking, enabling future HL-LHC experiments.
Paper reduces AI complexity with pre-defined sparsity and hardware acceleration.
problem Reduction of computational and storage complexity in neural networks.
method Pre-defined sparsity and hardware acceleration architecture.
result Significant reduction in storage and computational complexity (5X+ reduction) without significant performance loss.
Paper presents FPGA implementation for efficient recurrent neural networks.
problem Implementing recurrent neural networks on FPGAs for low latency.
method Developed hls4ml framework to implement LSTM and GRU layers.
result Demonstrated effective designs for both small and large models.
Memory-augmented neural networks (MANNs) are designed for question-answering tasks. It is difficult to run a MANN effectively on accelerators designed for other neural networks (NNs), in particular on mobile devices, because MANNs require recurrent data paths and various types of operations related to external memory a…
Real-time semantic segmentation for autonomous vehicles on FPGA reduces latency and power consumption.
problem Efficient real-time semantic segmentation for autonomous vehicles.
method Compressed ENet architecture, FPGA deployment, batch processing, filter reduction, quantization-aware training.
result Reduced latency to 3 ms per image with batch size of ten and 40% resource utilization.
New framework reduces cost of financial option pricing simulations on FPGAs.
problem Efficiently simulate financial option pricing with reduced computational cost.
method Nested MLMC framework with low precision calculations on FPGAs.
result Higher computational savings compared to existing mixed-precision MLMC frameworks.
PolyLUT uses polynomials to reduce FPGA latency.
problem Reducing latency in FPGA-based neural network inference.
method Training neural networks using multivariate polynomials as basic building blocks.
result Achieved significant latency and area improvements.
Recent work has shown that Field-Programmable Gate Arrays (FPGAs) play an important role in the acceleration of Machine Learning applications. Initial specification of machine learning applications are often done using a high-level Python-oriented framework such as Tensorflow, followed by a manual translation to either…
Efficient FPGA dropout algorithm reduces memory usage.
problem Overfitting in deep neural networks.
method Hardware-oriented dropout algorithm for FPGA implementation.
result Significant resource reduction in FPGA implementation.
FPGAs accelerate DNNs with binarized weights, improving power and speed.
problem Power and speed limitations of GPU-accelerated DNNs.
method Binarized neural networks on FPGAs using OpenCL.
result Near state-of-the-art performance with >16x power savings.
The rapid growth of data size and accessibility in recent years has instigated a shift of philosophy in algorithm design for artificial intelligence. Instead of engineering algorithms by hand, the ability to learn composable systems automatically from massive amounts of data has led to ground-breaking performance in im…
Kolmogorov-Arnold Networks enable ultrafast online learning with fixed-point quantization.
problem Efficient online learning for high-frequency systems with strict memory constraints.
method Fixed-point online training on FPGAs exploiting B-spline locality in KANs.
result Kolmogorov-Arnold Networks are more efficient and expressive than MLPs for low-latency tasks.
Hardware accelerations of deep learning systems have been extensively investigated in industry and academia. The aim of this paper is to achieve ultra-high energy efficiency and performance for hardware implementations of deep neural networks (DNNs). An algorithm-hardware co-optimization framework is developed, which i…
NeuraLUT maps neural networks to lookup tables, reducing latency and improving expressivity.
problem Reducing latency in deep neural networks for FPGA accelerators.
method Mapping entire sub-networks to a single lookup table, introducing skip connections.
result Up to 4.3x lower latency for the same accuracy.
A new method improves RVFL networks for resource-efficient machine learning.
problem Deploying machine learning on edge devices with limited resources.
method Density encoding and hyperdimensional computing operations.
result The proposed method achieves higher accuracy and lower energy consumption.
Trading system uses NP-hard optimization to select stocks for high Sharpe ratio trading.
problem Finding profitable, uncorrelated stocks for high Sharpe ratio trading.
method NP-hard combinatorial optimization using Ising machine and simulated bifurcation algorithm.
result Trading strategy with FPGA-based system achieves 164 μs response latency.
This paper proposes a learning framework for n-bit quantized neural networks that improves accuracy and speed on FPGAs.
problem Efficiently implementing quantized neural networks on FPGAs to maintain accuracy and speed.
method A novel learning framework for n-bit QNNs, constrained weights, reconstructed gradient function, n-BQ-NN structure, and SVPE array.
result Quantized models achieve almost the same accuracy as full-precision models and outperform typical low-precision QNNs.
Paper proposes NASAIC framework for co-designing neural architectures and heterogeneous ASICs.
problem Designing efficient neural architectures and ASICs for multiple tasks.
method Build ASIC templates and propose NASAIC framework for simultaneous design of architectures and ASICs.
result NASAIC ensures design specifications and maximizes accuracy with minimal performance loss.
This paper introduces channel gating, a dynamic, fine-grained, and hardware-efficient pruning scheme to reduce the computation cost for convolutional neural networks (CNNs). Channel gating identifies regions in the features that contribute less to the classification result, and skips the computation on a subset of the …
Reservoir computing is a neural network approach for processing time-dependent signals that has seen rapid development in recent years. Physical implementations of the technique using optical reservoirs have demonstrated remarkable accuracy and processing speed at benchmark tasks. However, these approaches require an e…
Efficient FPGA virtualization for deep learning reduces user isolation and overhead.
problem Poor isolation and heavy re-compilation overhead in FPGA-based DNN accelerators.
method Two-level instruction dispatch module, multi-core hardware resources pool, tiling-based instruction frame package, two-stage static-dynamic compilation.
result 1.07-1.69x and 1.88-3.12x throughput improvement over previous designs.
LUTNet optimizes FPGA neural network accelerators by leveraging LUTs for inference, achieving significant area savings.
problem Redundancy in deep neural networks and inefficient use of FPGA resources.
method End-to-end hardware-software framework using LUTs to implement any K-input Boolean operation for inference.
result Significant area savings and comparable accuracy compared to state-of-the-art binarized neural networks.
In this work, we design a machine learning based method, online adaptive primal support vector regression (SVR), to model the implied volatility surface (IVS). The algorithm proposed is the first derivation and implementation of an online primal kernel SVR. It features enhancements that allow efficient online adaptive …
New approach uses Boolean circuits to optimize neural networks.
problem Improving efficiency of neural network implementations on hardware accelerators.
method Formalized neural networks as Boolean circuits, showing binarized networks are functionally complete.
result Binarized neural networks are functionally complete, suggesting new possibilities for neural network accelerators.
LUTNet optimizes FPGA for neural network inference, achieving high efficiency.
problem Redundancy in neural networks leads to inefficient hardware implementations.
method Exploits LUTs' flexibility for efficient neural network inference on FPGAs.
result Significant area savings with comparable accuracy compared to state-of-the-art binarized neural networks.
PoET-BiN reduces power consumption in neural networks on embedded devices.
problem Power inefficiency in neural network implementations on embedded platforms.
method Look-Up Table based implementation with a modified Decision Tree approach.
result Near state-of-the-art results with up to 6 orders of magnitude energy reduction.
This paper improves neural network efficiency by combining filter columns and retraining, boosting array utilization and accuracy.
problem Efficient implementation of sparse convolutional neural networks on systolic arrays.
method Column combining of filter matrices, retraining of remaining weights, joint optimization for high utilization and accuracy.
result Significantly increased systolic array utilization efficiency (e.g., ~4x) and maintained high classification accuracy.
New methodology optimizes complex systems design trade-offs.
problem Complex multi-objective optimization with unknown feasibility constraints.
method Introduces HyperMapper 2.0 for multi-objective optimization, handling categorical/ordinal variables.
result HyperMapper 2.0 provides better Pareto fronts and 8x improvement in sampling budget.
Improves magnetic field mapping using an array of magnetometers with noisy input.
problem Improving magnetic field maps in indoor environments with noisy magnetometer data.
method Uses Gaussian process regression with an array of magnetometers, incorporating known array positions and relative magnetometer locations.
result The method produces higher quality magnetic field maps compared to using a single magnetometer.
SNRA combines power-efficient probabilistic and deterministic computing for deep belief networks.
problem Efficiently training and evaluating deep belief networks with low power consumption.
method Developed a spintronic neuromorphic reconfigurable array (SNRA) for in-circuit training and evaluation of deep belief networks (DBNs). Used probabilistic spin logic devices and a four-state finite state machine for unsupervised training.
result SNRA achieves more than 80% reduction in combined dynamic and static power dissipation compared to SRAM-based configurable fabrics.
In a previous work we have detailed the requirements to obtain a maximal performance benefit by implementing fully connected deep neural networks (DNN) in form of arrays of resistive devices for deep learning. This concept of Resistive Processing Unit (RPU) devices we extend here towards convolutional neural networks (…
We discuss of the conceptual difficulties connected with the anticommutativity of classical fermion fields, and we argue that the "space" of all classical configurations of a model with such fields should be described as an infinite-dimensional supermanifold M. We discuss the two main approaches to supermanifolds, and …
FPGA-based multi-layer equalizer adapts to changing channels.
problem Real-time adaptation to time-varying channel impairments.
method Multi-layer machine learning on FPGA with on-chip gradient backpropagation training.
result Real-time adaptation to changing channel conditions achieved.
TinyCNN accelerates CNN models on embedded FPGA with 15x speedup.
problem Limited memory on embedded FPGAs restricts CNN performance.
method Software and hardware design tool for FPGA resource-aware CNN accelerator.
result 3% accuracy loss with 15.75x speedup on image classification.
Recent results at the Large Hadron Collider (LHC) have pointed to enhanced physics capabilities through the improvement of the real-time event processing techniques. Machine learning methods are ubiquitous and have proven to be very powerful in LHC physics, and particle physics as a whole. However, exploration of the u…
Recurrent Neural Networks (RNNs), which are a powerful scheme for modeling temporal and sequential data need to capture long-term dependencies on datasets and represent them in hidden layers with a powerful model to capture more information from inputs. For modeling long-term dependencies in a dataset, the gating mecha…
Automated tool reduces FPGA inference latency to 5 μs for deep neural networks.
problem Deploying ultra low-latency, low-power deep neural networks on FPGAs.
method Extending hls4ml library, using model compression techniques like pruning and quantization-aware training.
result Achieved inference latency of 5 μs with 97% resource reduction.
Flexible VHDL design for multiple neural networks on FPGAs.
problem Inflexible neural network designs for FPGAs.
method Proposes a flexible VHDL structure with multiple processor groups.
result Allows training and testing of multiple neural networks on multiple FPGAs.
FPDeep accelerates CNN training on FPGA clusters with high parallelism and energy efficiency.
problem Scaling DNN training to large clusters with high utilization and balanced workload.
method Hybrid model and layer parallelism, fine-grained pipeline, balanced workload partitioning.
result FPDeep achieves high parallelism and utilization, reducing storage demand to on-chip memory.
A new method for verifying deep learning architectures on FPGAs is proposed.
problem Design-time verification of deep learning architectures on FPGAs.
method 2-Level 3-Way (2L-3W) hardware-software co-verification methodology.
result Layer-by-layer similarity scores of 99% accuracy for successful mappings.
CodeX improves DNN acceleration on FPGAs by encoding and customizing bitwidth.
problem Efficiently accelerating deep neural networks on FPGAs with limited memory.
method Nonlinear encoding, automated bitwidth customization, FPGA streaming buffers.
result Average 4.65x throughput improvement on MNIST, SVHN, CIFAR-10.
A lightweight FPGA-based reinforcement learning approach for edge devices.
problem Resource constraints and inefficiency of DQN on edge devices.
method OS-ELM based training algorithm and L2 regularization for stability.
result 29.77x and 89.40x faster than conventional DQN-based approach for CartPole-v0 task.
FPGA-based logic architecture speeds up GBDT training 259x.
problem Training efficiency and power consumption in GBDT models.
method Implemented logic architecture on FPGA, compared with software libraries.
result Training speed 26-259x faster, power efficiency 90-1,104x higher.
This paper designs sensor arrays for estimating unsteady flows efficiently.
problem Estimating high-dimensional unsteady flow fields with limited sensor placement.
method Combines data-driven modeling, Kalman Filter design, and sparsification for sensor selection.
result Proposed sensor arrays are highly effective for flow-field estimation across various conditions.
The paper proves existence of solutions for mean field equations on compact Riemann surfaces.
problem Existence of solutions for mean field equations on compact Riemann surfaces.
method Min-max scheme introduced by Djadli-Malchiodi (2006) and Djadli (2008).
result Proves existence of solutions for mean field equations on compact Riemann surfaces.
Gating units in GRUs and LSTMs create slow modes and control phase-space complexity.
problem Training challenges in RNNs due to exploding or vanishing gradients.
method Random matrix theory and mean-field theory applied to GRUs and LSTMs.
result Gates in GRUs and LSTMs lead to accumulation of slow modes and control phase-space complexity.
We present a design and implementation of the Thomas algorithm optimized for hardware acceleration on an FPGA, the Thomas Core. The hardware-based algorithm combined with the custom data flow and low level parallelism available in an FPGA reduces the overall complexity from 8N down to 5N serial arithmetic operations, a…