Research
On-device research index

arXiv research

A locally-built, LLM-digested index of recent arXiv papers in quant finance, geometry/topology, and statistical ML — keyword search served straight from SQLite on this machine.

168,657 papers · 148 categories

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19375674 · May 202619922001200920172026
48 results for AI hardware

HotNAS reduces AI search time from hundreds of GPU hours to less than 3 GPU hours.

problem High time required for AI solution generation from scratch.
method HotNAS starts from a 'hot' state using pre-trained models and integrates compression during co-search.
result Reduces search time from 200 GPU hours to less than 3 GPU hours.

Quantum circuits explained using Shapley values for better understanding.

problem Improving the explainability of quantum machine learning circuits.
method Applying Shapley values to quantify gate importance in quantum circuits.
result Quantum circuits can be explained by their gate importance, enhancing understanding and interpretability.

The MIT/IEEE/Amazon GraphChallenge.org encourages community approaches to developing new solutions for analyzing graphs and sparse data. Sparse AI analytics present unique scalability difficulties. The proposed Sparse Deep Neural Network (DNN) Challenge draws upon prior challenges from machine learning, high performanc…

2019-09-02abs ↗pdf ↗

Paper proposes efficient BNN inference flow to reduce computation and memory costs.

problem High computation complexity in Bayesian Neural Networks (BNNs) limits deployment in power-constrained systems.
method Feature decomposition and memorization strategy to reduce computations and a memory-friendly computing framework to reduce memory overhead.
result Reduces computation by about half and energy consumption by 73% with 14% area overhead.

FP6 quantization outperforms INT4 in diverse generative tasks for LLMs.

problem Limited performance of 4-bit quantization methods in diverse generative tasks.
method Proposes a 4+2 design for FP6 quantization to achieve similar latency to INT4.
result FP6 quantization outperforms INT4 in various generative tasks, including code generation and summarization.

In order to port the performance of trained artificial neural networks (ANNs) to spiking neural networks (SNNs), which can be implemented in neuromorphic hardware with a drastically reduced energy consumption, an efficient ANN to SNN conversion is needed. Previous conversion schemes focused on the representation of the…

2019-12-30abs ↗pdf ↗

Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timing-dependent plasticity (STDP) mechanism for learning. Existing hardware implementations of…

2018-09-18abs ↗pdf ↗

DANCE optimizes neural network and accelerator design for faster, more efficient DNN execution.

problem Challenges in optimizing neural network and accelerator design for efficient DNN execution.
method Differentiable approach to co-exploration of accelerator and network architecture design.
result Significantly shorter time to achieve superior accuracy and hardware cost metrics.

NEST optimizes deep learning training by placing devices efficiently across networks and memory.

problem Inefficient device placement in distributed deep learning leads to high communication and memory overhead.
method NEST uses network-, compute-, and memory-aware dynamic programming to optimize device placement.
result NEST achieves up to 2.43 times higher throughput and better memory efficiency.

Recent breakthroughs in Deep Learning (DL) applications have made DL models a key component in almost every modern computing system. The increased popularity of DL applications deployed on a wide-spectrum of platforms have resulted in a plethora of design challenges related to the constraints introduced by the hardware…

2018-09-14abs ↗pdf ↗

Method predicts hardware resource usage by control software with guaranteed linear convergence.

problem Predicting time-varying hardware resource availability in control software.
method Path structured multimarginal Schrödinger bridge (MSBP) for learning stochastic resource usage.
result Guaranteed linear convergence to accurate prediction of hardware resource utilization.

Quantum algorithms for CVaR portfolio optimization face trade-offs between hardware coherence and expressibility.

problem Quantum algorithmic resilience for CVaR portfolio optimization
method WS-QAOA vs. HE-VQNN
result WS-QAOA provides exact theoretical mapping but suffers from hardware decoherence, while HE-VQNN preserves hardware coherence but lacks expressibility.

This paper tackles co-design of neural hardware and software to improve efficiency.

problem Designing efficient deep learning systems that consider both hardware and software optimizations together.
method Developed a constrained Bayesian optimization framework to automatically identify profitable design points in the joint hardware/software design space.
result Improved energy-delay product by 18% (ResNet) and 40% (DQN) over hand-tuned systems.

APQ jointly optimizes neural architecture, pruning, and quantization for efficient inference.

problem Efficient deep learning inference on resource-constrained hardware.
method Joint optimization of neural architecture, pruning, and quantization policy using a quantization-aware accuracy predictor.
result Joint optimization leads to 2.3% higher ImageNet accuracy with reduced latency and energy consumption.

We derive scaling laws for optimizing neural networks in hardware.

problem Optimizing the large parameter space of neural networks in hardware.
method Analytical derivation of scaling laws for Coordinate Descent optimization.
result Convergence is exponential and scales linearly with the number of neurons.

This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementatio…

2014-09-09abs ↗pdf ↗

Optimized neural networks for Edge TPU achieve high accuracy in real-time image classification.

problem Designing neural networks for hardware accelerators to achieve optimal performance.
method Hardware-aware neural architecture search and model customization for Edge TPU.
result Improved accuracy-latency tradeoff on Pixel 4's Edge TPU compared to existing models.

With the rising popularity of machine learning and the ever increasing demand for computational power, there is a growing need for hardware optimized implementations of neural networks and other machine learning models. As the technology evolves, it is also plausible that machine learning or artificial intelligence wil…

2018-06-14abs ↗pdf ↗

SmallML predicts customer churn for SMEs with small data, improving accuracy by 24.2 points.

problem AI exclusion of SMEs due to data scale mismatch.
method Bayesian transfer learning with hierarchical pooling and conformal prediction.
result 96.7% AUC on 100 obs SMEs, 24.2 point improvement over logistic regression.

Paper presents efficient algorithms for convolutional neural networks using Winograd minimal filtering.

problem Resource-efficient implementation of convolutional neural networks.
method Winograd minimal filtering trick applied to M-tap filters (M=3,5,7,9,11) for parallel hardware implementation.
result Approximately 30% reduction in multipliers for fully parallel hardware implementation.

Hardware-accelerated RBM solves large combinatorial problems and integer factorization.

problem Solving large combinatorial optimization and integer factorization problems.
method Logically synthesized RBM architecture, hardware acceleration, and efficient training methods.
result Hardware-accelerated RBM factorizes 16-bit numbers with 10000x speed and 32x power improvements.

Quantum algorithm reduces CVA risk-neutral expectation estimation costs.

problem Reducing Monte Carlo sampling cost for CVA on real quantum hardware.
method Noise-aware quantum workflow combining market calibration, discretisation, and oracle construction.
result CABIQAE achieves lower classical post-processing runtime and more effective error exploitation.

Improves VQAs by balancing classical and quantum training resources.

problem Challenges in trainability and resource costs of VQAs on quantum hardware.
method Adopting HELIA Ansatz and combining classical and quantum methods for gradient estimation and training.
result Achieves higher accuracy and success rates in VQE and improved test accuracy in quantum phase classification.

Pipelined Backpropagation trains large models without batches efficiently.

problem Training large models efficiently on hardware with limited batch sizes.
method Fine-grained Pipelined Backpropagation with Spike Compensation and Linear Weight Prediction.
result Fine-grained Pipelined Backpropagation with a batch size of one matches the accuracy of SGD for multiple networks.

Resource-constrained IoT devices, such as sensors and actuators, have become ubiquitous in recent years. This has led to the generation of large quantities of data in real-time, which is an appealing target for AI systems. However, deploying machine learning models on such end-devices is nearly impossible. A typical so…

2019-07-31abs ↗pdf ↗

New algorithm reduces federated learning rounds and improves privacy.

problem Inefficient synchronous federated learning causing scalability issues.
method Asynchronous federated learning with reduced communication and differential privacy via Gaussian noise.
result The algorithm reduces waiting times and network communication, making federated learning more scalable and private.